1 thought on “In -depth report of the semiconductor industry: the peak of manufacturing, the wafer foundry track continues to prosper”
Bernard
TSMC opened the era of wafer workers and became the most important link in integrated circuits. In 1987, the establishment of TSMC opened the era of wafer foundry, especially after being certified by Intel, wafer foundry was accepted by more semiconductor manufacturers. The wafer foundry broke the IDM single mode and achieved the wafer foundry IC design mode. At present, the vertical division of labor in the semiconductor industry has become the mainstream. Most newcomers embrace Fabless models, and some IDM manufacturers are gradually moving towards Fabless or Fablite models. The global wafer foundry market has always showed rapid growth, and it is expected to continue in the future. After the wafer foundry IC design has become the industry trend, the strong demand for products in the Internet and mobile Internet era has remained rapidly growing. Taking TSMC as an example, its operating income increased from US $ 170 million in 1991 to 2019 in 2019 $ 34.6 billion, 1991-2019, CAGR was 21%. In 2019, the global wafer foundry market reached US $ 62.7 billion, accounting for about 15%of the global semiconductor market. In the future, in the era of the Internet of Things, under the demand for 5G, artificial intelligence, and big data, the wafer foundry industry is expected to maintain rapid growth.
DDODLE industry: The industry presents oligopoly concentration. Walls of foundry are the subversion of the manufacturing industry, showing the characteristics of high funding barriers, high technical difficulty, and fast technical iteration, which has also led to the industry's oligopoly concentration. Among them, TSMC is the absolute leader of the wafer foundry industry. The ratio of more than 50%, CR5 is about 90%. This foundation industry has high funding barriers. The capital expenditure of wafer factories is huge, and with the improvement of the process, the capital export center of foundries has been continuously increased. TSMC's capital expenditure increased from 44.3 billion yuan in 11 years to 109.4 billion yuan in 19 years, and CAGR was 12%. SMIC's international capital expenditure has increased from 3 billion yuan in 11 years to 13.1 billion yuan in 19 years, and CAGR is 20%. With the advancement of the 14 NM and N 1 process, the company will significantly increase capital expenditure in 2020. It is planned to be 45.5 billion yuan. The huge investment blocks many chaser outside the door, and it is very difficult for new entrants. With the improvement of the process, the difficulty of wafer foundry has increased significantly. With the improvement of the foundry process, technology needs to be comprehensively innovated in comprehensive innovation in the technology of crystal pipe technology, light carvings, sedimentation, etching, detection, and packaging, so as to support the performance of the chip performance of ceiling to achieve breakthroughs. The transistor process continues to innovate. The traditional transistor process is BULK SI, also known as the Planar FET. As the size of the MOS tube continues to become smaller, that is, the channels are constantly becoming smaller, and various problems will occur, such as many problems such as grid leakage and high leakage power. The main difference between the traditional MOS structure is that the SOI device has a buried oxidation layer and is usually SIO2, which isolate the substrate from the substrate. Due to the existence of the oxidation layer, the leakage path away from the gate can be eliminated, which can reduce power consumption. As the process continues to increase, the thickness of the conventional silicide oxide layer has become extremely thin. For example, the silicon dioxide layer in the transistor in the 65nm process has narrowed the thickness of only 5 oxygen atoms. It is difficult to further reduce the silicon dioxide layer, otherwise the leakage current generated will make the transistor cannot work normally. Therefore, in the 28nm process, the dielectric material of the High Saicap Creation (K) is introduced instead of the silicon oxidation layer (also known as HKMG technology). With the reduction of the size of the device, at lower technical nodes, such as 22nm, the short channel effect has begun to become more obvious, reducing the performance of the device. To overcome this problem, FinFET was born. The FinFET structure provides improved electrical control channel conduction, which can reduce the leakage current and overcome some short channel effects. At present, advanced programs adopt the FinFET structure. This process improvement, more fine chips, the performance of the lithography machine continues to improve. The core manufacturing equipment responsible for the "engraving" circuit pattern is a lithography machine. It is one of the core equipment in the chip manufacturing stage. The accuracy of the lithography machine determines the accuracy of the process. The fourth-generation deep ultraviolet light carved machine is divided into step-by-step scanning and scanning light engraving machine and an immersed step scanning projection light carved machine. Production of craft node chips. Through multiple exposure etching, the projection step scanning the projection light carvings can be achieved by 22/16/14/10nm chips. By the 7/5nm process, the DUV light carving machine has been difficult to achieve production and requires more advanced EUV lithography machines. EUV production is extremely difficult, with more than 100,000 parts and components, and only ASL in the world has production capacity. At present, EUV optical carvings are limited and the price is expensive. In 2019, ASML EUV has only 26 units, and a single EUV selling price is as high as US $ 120 million. This foundation technology is fast, which is conducive to head foundry. After the chip process enters the 90nm node, the technical iteration becomes faster, and the new process will appear almost every two to three years. Advanced processes not only need continuous R
TSMC opened the era of wafer workers and became the most important link in integrated circuits. In 1987, the establishment of TSMC opened the era of wafer foundry, especially after being certified by Intel, wafer foundry was accepted by more semiconductor manufacturers. The wafer foundry broke the IDM single mode and achieved the wafer foundry IC design mode. At present, the vertical division of labor in the semiconductor industry has become the mainstream. Most newcomers embrace Fabless models, and some IDM manufacturers are gradually moving towards Fabless or Fablite models.
The global wafer foundry market has always showed rapid growth, and it is expected to continue in the future. After the wafer foundry IC design has become the industry trend, the strong demand for products in the Internet and mobile Internet era has remained rapidly growing. Taking TSMC as an example, its operating income increased from US $ 170 million in 1991 to 2019 in 2019 $ 34.6 billion, 1991-2019, CAGR was 21%. In 2019, the global wafer foundry market reached US $ 62.7 billion, accounting for about 15%of the global semiconductor market. In the future, in the era of the Internet of Things, under the demand for 5G, artificial intelligence, and big data, the wafer foundry industry is expected to maintain rapid growth.
DDODLE industry: The industry presents oligopoly concentration. Walls of foundry are the subversion of the manufacturing industry, showing the characteristics of high funding barriers, high technical difficulty, and fast technical iteration, which has also led to the industry's oligopoly concentration. Among them, TSMC is the absolute leader of the wafer foundry industry. The ratio of more than 50%, CR5 is about 90%.
This foundation industry has high funding barriers. The capital expenditure of wafer factories is huge, and with the improvement of the process, the capital export center of foundries has been continuously increased. TSMC's capital expenditure increased from 44.3 billion yuan in 11 years to 109.4 billion yuan in 19 years, and CAGR was 12%. SMIC's international capital expenditure has increased from 3 billion yuan in 11 years to 13.1 billion yuan in 19 years, and CAGR is 20%. With the advancement of the 14 NM and N 1 process, the company will significantly increase capital expenditure in 2020. It is planned to be 45.5 billion yuan. The huge investment blocks many chaser outside the door, and it is very difficult for new entrants.
With the improvement of the process, the difficulty of wafer foundry has increased significantly. With the improvement of the foundry process, technology needs to be comprehensively innovated in comprehensive innovation in the technology of crystal pipe technology, light carvings, sedimentation, etching, detection, and packaging, so as to support the performance of the chip performance of ceiling to achieve breakthroughs.
The transistor process continues to innovate. The traditional transistor process is BULK SI, also known as the Planar FET. As the size of the MOS tube continues to become smaller, that is, the channels are constantly becoming smaller, and various problems will occur, such as many problems such as grid leakage and high leakage power. The main difference between the traditional MOS structure is that the SOI device has a buried oxidation layer and is usually SIO2, which isolate the substrate from the substrate. Due to the existence of the oxidation layer, the leakage path away from the gate can be eliminated, which can reduce power consumption. As the process continues to increase, the thickness of the conventional silicide oxide layer has become extremely thin. For example, the silicon dioxide layer in the transistor in the 65nm process has narrowed the thickness of only 5 oxygen atoms. It is difficult to further reduce the silicon dioxide layer, otherwise the leakage current generated will make the transistor cannot work normally. Therefore, in the 28nm process, the dielectric material of the High Saicap Creation (K) is introduced instead of the silicon oxidation layer (also known as HKMG technology). With the reduction of the size of the device, at lower technical nodes, such as 22nm, the short channel effect has begun to become more obvious, reducing the performance of the device. To overcome this problem, FinFET was born. The FinFET structure provides improved electrical control channel conduction, which can reduce the leakage current and overcome some short channel effects. At present, advanced programs adopt the FinFET structure.
This process improvement, more fine chips, the performance of the lithography machine continues to improve. The core manufacturing equipment responsible for the "engraving" circuit pattern is a lithography machine. It is one of the core equipment in the chip manufacturing stage. The accuracy of the lithography machine determines the accuracy of the process. The fourth-generation deep ultraviolet light carved machine is divided into step-by-step scanning and scanning light engraving machine and an immersed step scanning projection light carved machine. Production of craft node chips. Through multiple exposure etching, the projection step scanning the projection light carvings can be achieved by 22/16/14/10nm chips. By the 7/5nm process, the DUV light carving machine has been difficult to achieve production and requires more advanced EUV lithography machines. EUV production is extremely difficult, with more than 100,000 parts and components, and only ASL in the world has production capacity. At present, EUV optical carvings are limited and the price is expensive. In 2019, ASML EUV has only 26 units, and a single EUV selling price is as high as US $ 120 million.
This foundation technology is fast, which is conducive to head foundry. After the chip process enters the 90nm node, the technical iteration becomes faster, and the new process will appear almost every two to three years. Advanced processes not only need continuous R